Computer set point station

ABSTRACT

A device for interfacing a computer with an analog control system to control processes. The controlling computer changes the digital set point values in various control stations by addressing the individual station, zeroing the set point value and inserting the new value.

United States Patent Johnson et al.

[ Sept. 19, 1972 [54] COMPUTER SET POINT STATION [72] Inventors: IrvinD. Johnson, Englewood, Colo.;

Mauro G. Togneri, Houston, Tex.; Eduard P. Kaufmann, Burghausen,

Germany Pn'mary Examiner-Harvey E. Springbom [73] Assignee: Marathon OilCompany, Findlary, Attorney-Joseph C. Herring, Richard C. Wilson, Jr.

Ohio and Jack L. Hummel [22] Filed: Oct. 2, I970 57 ABSTRACT PP 77,510 Adevice for interfacing a computer with an analog control system tocontrol processes. The controlling 52 us. Cl. ..34o/172.s Computerchanges P0int values 51 Int. Cl. ..G05b 15/00, G06f 3/00 Comm] Swim byaddressing the individual [58] Field of Search ..34o/172.5, 146.1Zeroing the set P value and inserting the new value.

[561 17 Claims, 7 Drawing Figures UNITED STATES PATENTS 3,58] ,2895/1971 Wilhelm et al. ..340/l72.5

'MULTlC0NDUCT0R CABLE 1 SET POIN; INPUT GATING CONDUCTOR3Z l COMPUTERSET POINT 2O STATION MEMORY lNTERLOCK OSCILLATC? Dl6lTAL-TO-ANALOGCOMPUTER" 3 '7 A CONIYIEGZTAEPIQD LOW 2i 3| 38,39 CLOCK CONDUCTOR33-\D/A OUTPUT LINE ADJUSTMENT l ZERO cououcron CONDUCTOR 65 VARIABLE VQ g; .::.s:% 2%l'l3zlS 53,156? TERMMUFF, comm. LOGIC ADJUSTMENTFAIL-SAFE 27 1 L 4| MONITOR [40 1: LL OMPARATOR F63 ADDRESS 82 *9 25aLOGIC $235 compurzn CT STATUS CONDUCTOR LAMP ANALOG CONTROLLER CONDUCTORPATENTEDsEP 19 1912 3,693,163 SHEETIOF'! EX i k m 9 N (O 1 A I I l wl N1 4 l V 9h & \1

INVENTORS IRVIN D. JOHNSON MAURO G. TOGNERI INVENTORS IRVIN 0. JOHNSONMAURO G.TOGNERI PMENTEDSEP 19 I972 sum 5 (IF 7 PATENTEI JSEP 19 9 BB1AVAILABLE COPY SHEET 8 0F 7 INVENTORS IRVIN D. JOHNSON MAURO G TOGNERIfiEDU R P. KAUFMANN BY .4

PATENTED EP 1 912 3.693; 1 63 SHEET 7 BF 7 INVENTORS IRVIN D. JOHNSONMAURO G. TOGNERI E AR RKAUFMANN M COMPUTER SET POINT STATION CROSSREFERENCES TO RELATED APPLICATIONS The only related pending patentapplication of which the inventors are aware is Ser. No. 623,015 filedMar. 14, 1967, now US. Pat. No. 3,548,169 issued Dec. 15, 1970.

BACKGROUND OF THE INVENTION 1. Field of the Invention The presentinvention relates to methods for control of physical and chemicalprocesses, particularly by digital computers controlling analog typeactuators, e.g., valves by acting through the interfacing device of thepresent invention.

2. Description of the Prior Art The most commonly used device forproviding an interface between a digital computer and an analogactuator, e.g., a valve, is a motor driven potentiometer such as thoseavailable commercially from a number of manufacturers. See for example,Spec. Sheet 98570-81 1 1-58, Taylor Instrument Co., Rochester, NY. Thesepotentiometers are subject to wear because they involve moving parts,particularly parts in slidable contact. Further, these potentiometersrequire considerable computer time since the computer must address thepotentiometer during the entire period over which the potentiometeradjustment occurs.

SUMMARY OF THE INVENTION The present invention avoids completely theneed for moving parts by using, in preferred embodiments, entirelysolid-state devices. The invention can be utilized as the interfacingdevice between a computer and a standard analog control system. In thismethod the output from the interfacing device of the invention operatesas the set point input to a standard analog controller, preferably arecorder-controller. Alternatively, the devices of the invention can beused directly as direct digital control units by sending their outputdirectly to the control valve or other analog device to be actuated.

Other advantages of the invention are:

1. Automatic bumpless transfer from manual set point adjustment tocomputer set point adjustment.

2. Digital memory, capable of holding value indefinitely.

3. Parallel input from computer. The memory in the unit can be updatedin less than 1 millisecond.

4. High and low limits can be set to prevent the process from exceedingsafe limits.

5. Maximum "rate of change" is settable in the unit to prevent astep-function from upsetting the process.

6. Fail-safe monitor-if the unit fails, the set point is automaticallytransferred back to the local set point adjustment in the analogcontroller. Controller and computer indicate such failure immediately.

7. Controller status lamp comes on only after the computer actuallyaddresses the unit providing positive check on operation.

8. Computer address of the unit is wired into card position so identicalunits are interchangeable.

9. Minimum computer outputs, e.g., 21 and time (1 millisecond per unit)to control up to 1,024 units or more.

l0. Galvanic isolation between the computer including the invention andthe process controllers with associated equipment.

Briefly stated, the invention involves methods and devices forconverting output from a digital computer to operate an analog controlsystem by successively changing the digital set point values in two ormore analog control stations by first addressing the individual analogcontrol station, then zeroing the set point value of the particularcontrol station addressed and inserting the new digital set point valueinto the control station addressed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showingthe control system of the present invention operating on the physicalcomponents of a process system.

FIG. 2 is a block diagram of the components of the control system of thepresent invention.

FIG. 3 is a diagram of the circuitry of the set point input valve gating19 and of the memory 20 and digitalto-analogue converter 21 shown inFIG. 2.

FIG. 4 is a diagram of the circuitry of the DC-DC converter 25, rate ofchange adjustment 43, oscillator 26, and high low limit adjustment 24,of the control system in FIG. 2.

FIG. 5 is a diagram of the circuitry of the variable address terminal14, address logic 15, of the control system shown in FIG. 2.

FIG. 6 is a diagram of the circuitry of the control logic l6, andanalogue comparator 18, shown in FIG. 2.

FIG. 7 is a diagram of the circuitry of the fail-safe monitor of controllogic 16 of the control system shown in FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. I, the control systemof the present invention is used to control a typical process system inwhich components A and B flow into reactor 1. Component A flows throughorifice plate 2. Differential pressure transducer 3 measuresdifferential pressure (and thus flow) across the orifice plate. Flowcontroller 4 is an analog type of flow controller having a conventionalremote set point input connected to computer set point station (CSPS) 5.Controller 4 is connected to flow control valve 6 throughcurrent-to-pressure converter 7.

A similar set point station (CSPS) 8 is connected to a similarcurrent-to-pressure converter 9 and pneumatically operated control valve10, all acting on component 8. Pressure transducer 11 and flowtransducer 3 are both connected back to computer 12 which acts throughthe system of the invention to control the process. The temperaturetransducer 13 is also connected to the computer to feed back thetemperature of reactor 1.

In operation, the system of FIG. 1 causes component A to flow throughorifice plate 2 causing a differential across flow transducer 3 which istransmitted back to computer 12. Similarly, component B flows past pressure transducer 11 which transmits a signal back to computer 12. Thetemperature transducer 13 measures the temperature in reactor 1 andtransmits the temperature signal back to computer 12.

The computer analyzes these three inputs of flow, pressure andtemperature, respectively, and, following a conventional process controlprogram, calculates the optimum setting for flow control valve 6. Thecomputer then digitally addresses CSPS 5 and, when the computer hasaddressed and been connected to that set point station, zeroes anyprevious digital set point contained in CSPS 5 and then transmits thenew recalculated optimum set point into the memory of CSPS 5. CSPS 5then gradually changes the digital set point in analog controller 4until it conforms with the newly calculated optimum set point which iscontained in the memory of CSPS 5. This gradual changing of the analogcontroller set point avoids bumps or discontinuities in process control.Analog controller 4 correspondingly adjusts its electrical output signalwhich is converted to a pneumatic signal by amperage-to-pressureconverter 7 so that valve 6 gradually moves to a new position.Simultaneously, analog controller 4 continuously senses the flow fromflow transducer 3 and continues to move valve 6 until the flow throughorifice plate 2 equals the newly calculated optimum set point.

After computer 12 has addressed, zeroed and transmitted the new setpoint to set point station 5, it breaks the connection with CSPS 5 andaddresses computer set point station 8. The previous set point value inCSPS 8 is zeroed and a new digital set point value (calculatedapproximately simultaneously with the optimum set point value for CSPS 5and stored briefly in the memory of computer 127, is inserted into CSPS8. Computer set point station 8 then transmits an amperage signal whichis converted to pressure in converter 9 and transmitted to valve 10.Thus, CSPS 8 acts directly upon valve 10 and varies its position. Thecomputer receives the new pressure signal from transducer 11, comparesit to the newly calculated optimum pressure, readdresses, rezeroes andreadjusts the digital set point in set point station 8 as necessaryuntil the signal received from pressure transducer 1] equals the newlycalculated optimum pressure. It should be noted that the set point whichthe computer transmits to CSPS 8 is in terms of valve position and thecomputer itself determines whether or not this valve position is thecorrect position to achieve the optimum pressure. This "direct digitalcontrol" is in contrast to the computer cascade analog control system"which is controlled by computer set point station 5. CSPS 5 resets anotherwise independent analog control loop to optimize the value at whichit controls with the rest of the system. Set point station 8 merelypositions the valve and the computer itself checks on whether thisposition provides the optimum pressure. While the control system used oncomponent A has the advantage of being self-sufficient in case ofcomputer failure, the direct digital control utilized for the pressurecontrol on component B ofiers major economic advantages by theelimination of the additional cost of the analog control loop.

Referring to FIG. 1, it will be noted that a single multiconductor cable29 connects the computer with both computer set point control stations.The use of this single multiconductor cable with the CSPS terminalsconnected in parallel is perrrtitted by the addressing feature of theinvention.

The circuitry of CSPS 5 or 8 (which are identical except for the hardwired addresses" discussed below) is shown schematically as a blockdiagram in FIG. 2. The circuitry of each of the blocks of FIG. 2 isshown in more detail in FIGS. 3 and following which are discussed laterin this application.

In FIG. 2 computer 12 is connected to variable address terminal 14 whichcontains a hard-wired" address which constitutes the digital address ofthe particular set point station. The variable address 14 is connectedthrough address logic 15 to control logic 16 which feeds a "ready"signal back to the computer through interlock l7, and which alsoreceives the reset signal to provide bumpless" transfer from local(noncomputer controlled) operation to computer controlled operation. Thecircuitry of elements 14 through l5, 16, 17 and 18 is shown in moredetail in FIGS. 5, 6 and 7, respectively.

Control logic 16 is connected to set point input gating 19 so that whenthe particular CSPS is addressed through elements 14 and 15, controllogic l6 responds by signalling set point input gating l9 and resetsCSPS memory 20. This permits the incoming signal from line 22 to enterthrough gating 19 into memory 20. Since the signal from the computer isin digital form, it is necessary to provide a digital-to-analogconverter 21. On transfer from local to computer set-point, the analogcontroller set-point is initially sent to comparator 18 for comparisonwith the set point which was previously set on the analog controller 4while in the local mode. In normal operation, the output form thedigital-to-analog converter 21 feeds through rate of change adjustment23, high and low limit adjustment 24 and DC-to-DC converter 25 into theremote set point located in analog controller 4. Oscillator 26 providesa ramping to element 20 on the switch-over from local to computercontrol, provides a clocking pulse to control logic l6 and provides achopping of the DC signal from DC to DC converter 25 in order to provideisolation of the output from that element. Fail-safe monitor 27 returnsthe analog controller 4 to the local mode upon any failure within thecomputer control system. (This fail-safe feature is inoperative indirect digital control.) Computer status lamp 28a is lit whenever theCSPS is under computer control.

FIG. 3 shows the circuitry of set point input value gating 19, memory20, and digital-to-analog converter 21. In FIG. 3, the digital memorycircuit systems F-l through F-ll are bistable circuits (flip-flops")which permit two modes of operation. In the first mode of operation, aone" signal enters through zero conductor 31 and conductor 32 is strobed(that is, its voltage is raised from a high to a low value for a shorttime period, e.g., 15 milliseconds). This strobing opens NOR-gates G-lthrough 6-10, allowing signals from the multiconductor cable 22(composed of 10 separate conductors 22-A through 22-!) to entercorresponding flip-flops F-l through F40. Transistors T-0 through T-l0then translate the binary value, which has entered, into an analog valuewhich is transmitted through operational amplifier A-l intodigital-toanalogue (D/A) output line 33, also shown on FIGS. 2, 4, and6. A voltage divider comprising resistors 34 and 35 and relays b-6 andb-9 closes the loop and provides a feed-back signal for monitoring bythe computer. The above-described mode is conveniently termed thecomputer-control mode" of the CSPS and is the normal mode duringoperation of the control system.

The second mode of the memory section of the CSPS is utilized inswitching from local control to computer control, and is termed thescaling up mode of the CSPS memory. The memory is placed into thescaling up mode by a zero pulse arriving through count-enable conductor38 and a zero-one-zero counting pulse arriving through clock conductor39. The flip-flops F-l through F-lO begin counting the clock pulse fromconductor 39 and continue to count until the voltage output of D/Aoutput 33 becomes equal to the voltage of the controller set point inconductor 40. This equality is determined by feeding both of thesevoltages to comparator 18. When comparator l8 senses that the twovoltages are equal it sends a high value through the conductor 48 whichis normally at a low voltage, discontinuing the clock pulse input toline 39. The signal to count-enable conductor 38 is automaticallydiscontinued approximately 150 milliseconds after it begins. This secondmode permits bumperless transfer from local to computer control. Theentire scaling up" mode will usually be accomplished in less than 100milliseconds.

In FIG. 3, flip-flop F 11 is an overranging logical device utilized inthe scale up mode" to permit overranging of the set point value up to asmuch as 200 percent of the set point value transmitted by the computer.Its function is to prevent constant recycling which would result from aminor discrepancy between the values in conductors 33 and 40,respectively.

FIG. 4 shows the circuitry of rate of change adjustment 43, high and lowlimit adjustment 24, DC-to-DC converter 25 and an oscillator 26.

In FIG. 4, resistor 42 and capacitor 43 limit the maximum rate of changeat which the output from D/A output conductor 33 is transmitted tooperational amplifier A-2 located within the DC-to-DC converter 25. Aswitch 44 permits selecting various alternate capacitors 43-A through43-C to vary the maximum rate at which the signal is inputted tooperational amplifier A2. In general, the input period rate will be inthe range of from one second to one-thousand seconds, but is notnarrowly critical and will preferably be matched to accommodate the rateof change encountered in the process which is being controlled.Transistor 45 compares the voltage on the slider arm 46 of a variablepotentiometer which had previously been preset to the lower limit of therange of computer control. For example, the rate of the potentiometercan be set at a value corresponding to 50 percent of the control valueand the computer will not control the process if the value of thatparameter falls below 50 percent of the control value. If the computerattempts to input to the CSPS a control point which is lower than thelower limit preset into potentiometer slider arm 46, the control pointcorresponding to the lower limit will automatically be inputted intocontroller 4. Similarly, transistor 47 compares the voltage beinginputted to operational amplifier A-2 with the voltage of the slider arm48 of a variable potentiometer, thus providing a high level limit on therange of computer control. Normally, the values of the high and lowlevel will be selected according to the safe range which the parametermay have in the process.

Control station 4 is galvanically isolated from the CSPS by means oftransformer 49 (having secondaries 49b, shown on FIG. 7 and 49a, shownin FIG. 4), in

order to permit the control station output to float without reference toground and to isolate the control station 4 from any short within theCSPS. To permit the galvanic isolation, the DC signal from operationalamplifier A-2 is converted to AC by transistors 50 and 51 which aredriven by oscillator 26, outlined with broken lines in FIG. 4 and alsoshown in block diagram F IG. 2. Within oscillator 26, resistor 52,capacitor 53, unijunclion transistor 54 and base resistors 55 and 56form a unijunction relaxation oscillator having an output of 20 Hz whichis divided by 2 and squared by flip-flop F-l2. The output from theflip-flop is amplified by bufier amplifiers 57 and 58. Isolation isprovided by capacitor-resistor pairs 59-60 and 61-62. An unlimitedsignal is fed through conductors 63 to control logic 16. The necessaryrectification of the AC signal from transformer 49 is provided by arectifier 64 and the rectified signal is sent to controller 4 throughconductors 65-A and B. Relays B-4 and B-5 provide an output monitor tothe computer in a manner similar to that provided by relays B-6 and B-9(shown in FIG. 3). All of the output monitor relays are actuatedsimultaneously and thus may be combined electrically, if convenient.

Relay B-3 bypasses resistor 42 to provide fast in put throughoperational amplifier A-2 when the CSPS memory is in the scale-up modedescribed above.

FIG. 5 shows the circuitry of the variable address 14 and the addresslogic l5. Terminal block 14 is wired with the unique digital address ofthe CSPS. The address shown wired in FIG. 5 is l l l." The terminalslabeled 1 through 128 connect through multlconductor address cable(similar to cable 22) with the corresponding terminals of the computerECO" (electronic contact operate) which comprises a series of switchesoperated in response to the programming of the computer.

While the IBM model 1800 computer is utilized with the particularcontrol system described herein, virtually any digital computer equippedwith a suitable ECO and having memory and other data processing abilityadequate to control the physical system, can be util ized.

A specific description of the IBM 1800 computer and its "ECO" appears inthe Physical Planning Manual for the IBM 1800, file number l800-l5, formnumber A26-5922-1, particularly pages 48-50, published by IBM, San Jose,Calif. 951 I4.

In FIG. 5, the address logic 15 contains the logic gate necessary todecode the address. NOR gates 67A through 67D decode the address fromvariable address 14. If the address signal from the computer ECO isidentical with the address hard wired into the variable address 14, theNOR-gates of the address logic 15 output a signal to address-selectconductor 66 (also shown on FIG. 2). This signal continues so long asthe computer ECO continues to transmit the address, generally for aboutID to 15 milliseconds. This pulse closes the contact on monitor relaysb-4, b-S, b-6 and b-9, causing feedback to the computer through theserelays. The signal in conductor 66 also is transmitted to control logic16 causing the control logic to permit response to the reset signal (ifany) on conductor 28 (shown in FIG. 6). The signal on conductor 66 alsocauses control logic 16 to be responsive to any set point value whichmay be transmitted while conductor 66 is energized. In

operation, control logic 16 does not respond to any reset pulse or anynew set point unless both such signals are preceded by a signalcorresponding to the address hard wired into variable address 14. Onlywhen an address signal corresponding to the address of variable address14 is first received, decoded by address logic l and conductor 66energized, does control logic 16 respond to reset signals transmittedthrough conductor 28 or new set points transmitted through conductor 22.Pull-up resistors 68 and 69 can have 1,000 ohms or other suitablevalues.

it is this addressing characteristic of the circuitry which permits allof the CSPSs to be connected to the computer in parallel by means of asingle multiconductor cable.

FlG. 6 describes the circuitry of control logic l6 and (outlined withdotted line) comparator 18. Hold up resistor 70 and NOR-gates 71 and 72permit control logic 16 to respond to a reset signal on conductor 28only when address select conductor 66 is energized. in operation,conductor 66 is energized upon an appropriate address being received byvariable address 14 and address logic l5. NOR-gate 72 then has an outputof zero. The reset signal from conductor 28 and the zero signal fromNOR-gate 72 are both received by NOR-gate 71 which responds byenergizing conductor 73 with a signal which is inverted by bufferamplifier 74 and transmitted to value gating conductor 32 which conductsthe signal to set point input value gating 19, also shown in F I05. 2and 3.

Capacitor 75, NOR-gate 76, buffer amplifier 77 and resistor 78 togetherform a single-shot multi-vibrator. in response to the energizing ofconductor 73, this single-shot multi-vibrator sends a short durationpulse (approximately 0.1 millisecond) to zero conductor 31, also shownin FIG. 3. This pulse resets CSPS memory to zero. NOR-gates 79, 80, and81 form a latching circuit. in response to an output signal fromNOR-gate 72, NOR-gate 79 transmits a signal to NOR-gate 80 which, inconjunction with NOR-gate 81, acts as a latch to continuously energizeconductor 82 causing computer status lamp 28a (shown in FIGS. 1 and 7)to light, indicating that the particular CSPS has been addressed and isunder computer control. During addressing by the computer, the signalfrom conductor 66 also goes to NOR-gate 83 energizing conductor 84 whichenergizes relay coils 8-4, -5, -6, and -9, closing the correspondingrelays b-4, 5, 6 and -9, causing feedback signals as described above.

Conductor 85 connects to one side of NOR-gate 81 and one side ofNOR-gate 86 which outputs through resistor 87 and time-delay capacitor88 into one side of NOR-gate 89 which itself outputs into one side ofNOR-gate 79, previously described. When the local controller is in thelocal position conductor 85 is energized at a "one" level, thus NOR-gate79 prevents the lighting of the computer status lamp.

NOR-gate 90 outputs through capacitor 91 and resistor 92 to one side ofNOR-gate 76, previously described. Elements 91, 92, and 76 thus comprisea single shot multivibrator which generates a 0.l millisecond signal inzero conductor 31, resetting the memory of control logic to zero at theinstant when controller status conductor 85 is deenergized by manuallyswitching the controller from local to the computer control mode.

NOR-gate 93, capacitor 94, NOR-gate 95, resistor 96 together comprise asingle shot multivibrator generating a 150 millisecond pulse into oneside of NOR-gate 97 at the instant that conductor is deenergized bymanually switching to the computer control mode.

This pulse goes to NOR-gate 97 and buffer amplifier 98, bringingcount-enable conductor 38 to a zero logic level for 150 milliseconds,permitting control logic memory to operate in the scale-up mode. Thesame pulse from bufier amplifier 98 also gates NOR-gate 99. NOR-gates 99and 100 are in parallel so that the pulse to NOR-gate 99 gates NOR-gate100 admitting the IQ KHz signal to clock conductor 39. The pulse fromNOR-gate 97 also passes through resistor 10! energizing relay coils 8-1,8-2, and B-3 (shown in FIG. 7).

The circuitry of comparator 18 is outlined with a dotted line in FIG. 6.When conductor 102 is energized with a one signal, relay coils 8-], 8-2and B-3 (shown in FIG. 7) operate transfer contacts b-] and b-2, (shownin FIG. 6) and b-3 (shown in FIG. 4). Operational amplifier 103 thenreceives a voltage pulse from capacitor 104. This voltage pulse which isindicative of the set point value then set in the analog controller, iscompared with the output from the digital-to-analog converter 21, whichis inputted to the operational amplifier 103 acting through scalingresistors 105 and 106. So long as the voltage pulse from capacitor 104(the controller set point value) is greater than the digital-toanalogconverter output in conductor 33, operational amplifier 103 will outputa zero signal through resistor 126 into one side of NOR-gate 100admitting the IQ KHz signal from conductor 63 to clock conductor 39.This causes scaling up of the value in the CSPS memory 20. A zener diode127, connected to ground limits the voltage between operationalamplifier 103 and NOR- gate 100.

When control logic memory 20 is in the scale-up mode, activating(closing) relay b-3 allows capacitor 43 to charge rapidly throughresistor 109 (both shown in FIG. 4). 0n initial transfer to computercontrol mode, this allows rapidly bringing the output of the CSPS onconductors 65-a and 65-h into equality with the locally set set-point onconductors 40-0 and 40-h, thus providing bumpless" transfer from thelocal to the computer control mode.

FIG. 7 shows the circuitry of interlock l7 and a remaining portion ofthe circuitry of control logic l6.

Relays b-l through b-7 and b-9 have been previously discussed above.

A warning of failure of a CSPS is provided by conductor 107 whichenergizes relay coil B-8 sending a continuous signal indicative offailure to the controller and returning the controller automaticallyinto local mode. A pulse is directed back to the computer throughconductor 107 at the start of each time when the CSPS is addressed bythe computer. Various accessory circuits may be added to provide "ready"or additional "failure" signals to the computer which can be programmedto respond in accordance with various emergency procedure programs.

When line 107, described above, is energized, NPN- transistor 110 admitscurrent to conductor 1 ll sending a ready" signal back to the computer.Output to controller 4 is monitored by the second of the secondarywindings 49-8 of the transformer (the primary and other secondary ofwhich are shown in FIG. 4). This output is rectified by bridge rectifier112 and fed to operational amplifier 113 and compared with a referencevoltage established by resistors 114 and 115. if the output voltagedrops below the preset limit set by the resistors, operational amplifier113 will latch in the up mode due to the positive feed back throughdiode 116 and resistor 117, thus placing a positive voltage on conductor118 and deenergizing relay coil B-S, turning on monitor failure lamp119, indicating failure of the particular CSPS.

Conventional commercially available circuitry components may be employedwith the invention. For example, the operational amplifiers canconveniently be Model No. SQ 10A manufactured by Nexus of Canton, Mass.and described in their brochure PB-l03a- 9/66( 1966914 manufactured byFairchild, and flip-flops can be Model No. 923 manufactured by Fairchildand described in their brochure BR-BR-00l5-29-100M, Library of CongressCat. No. 75-8731 l( 1969), control stations can be Model No. 940R,manufactured by Taylor and described in their brochure 98569Sl( 1969),File ll-SA. Conventional power and ground connections to the variouscomponents should be supplied where conventionally required, e.g., tothe NOR-gates. In general, the conventional techniques of computercontrol of set points and direct digital control by computer areapplicable to the present invention, see, for example, Computer Controlof Industrial Process by ES. Savas, McGraw-Hill (1965), Computer ProcessControl by Lee A. Gaines, and Mathematical Modeling in ChemicalEngineering by R. G. E. Franks, John Wiley and Son I967).

MODIFICATIONS OF THE INVENTION It should be understood that theinvention is capable of a variety of modifications and variations whichwill be made apparent to those skilled in the art by a reading of thespecification and which are to be included within the spirit of theclaims appended hereto. For example, all of the CSPS can be linked inparallel to a continuous loop multi-conductor cable, expanding over alarge area employed by the process plant, which is connected back toitself just prior to the connection to the computer. Such a loop willcontinue to provide control to each of the CSPS spread throughout theplant, even if it is broken at any single point along its length.Further, the loop can be extended by merely breaking the loop and addingsections where desired without taking any of the CSPS out of service. Ashas been previously stated, the CSPS can be utilized for direct digitalcontrol rather than operating through an analog station as described insome portions of the specification. Instead of the multiconductor cable,a single conductor cable may be utilized if a shift-register" isinstalled in each CSPS. Such a shift register receives the addresssignal as a series of pulses from the signal conductor and directs eachpulse to a different logical component of the shift register. After allpulses have been received, they are then simultaneously transmitted tothe CSPS which then operates as described above for a multiconductorcable installation. By utilizing a carrier wave signal to conduct thepulses into the shift register, the ordinary utility wiring can be usedto carry the signals. CSPSs can then be plugged into any normalconvenience outlet in the installation affording a high degree ofportability where desired.

An analogous design using AND-gates in place of the NOR-gates can besubstituted; a very wide variety of process components as well asmachines can be controlled by the invention, the collectors and emittersof the individual transistors can be transposed in the circuitry.

What is claimed is:

1. Apparatus for interfacing a digital computer with a control systemcomprising in combination,

a. a digital computer controlling the system in response to inputsreceived from various sensors indicative of conditions within variouspoints in the system, said computer having means for outputting aselective digital address signal and associated command signals,

. a multiplicity of control stations, each of said control stationshaving means for controlling at least one variable of the system inresponse to one of said command signals indicative of a desired controlpoint value for that variable,

c. common cable means for receiving said selected digital address signaland associated command signals outputted by said computer means, saidcable means being connected to a plurality of said control stations,

. prewired address means in each of said control stations which isdistinct from similar prewired addresses of other of said controlstations,

d. comparator means in each said control stations for comparing theaddress outputted by said computer with said prewired address,

f. address logic means for permitting said digital command signals to betransmitted from said computer to said memory means, within a particularcontrol station, when, and only when, said command signals areassociated with an address signal corresponding to the prewired addressof said particular control station,

g. zeroing means in each said control station for ze roing said memorymeans in response to an appropriate zero command signal from saidcomputer,

h. memory means in each said control station for storing said desiredcontrol point value transmitted from said computer.

2. The apparatus of claim 1 wherein there is further provided:

i. rate of change limiting means for controlling the transmission ofsaid signal from said memory to said control station so that the controlvalue signal inputted to said control station changes at a rate not inexcess of a predetennined maximum rate of change whereby said newdigital control value is gradually applied to said system.

3. The apparatus according to claim 2 wherein the rate of changelimiting means comprises capacitive means having a preselected timeconstant corresponding to the desired maximum rate of change.

4. The apparatus according to claim 1 wherein the signal outputted bysaid computer is transmitted to said comparator by means of amulti-conductor cable connected to a plurality of said addresscomparators.

5. The apparatus according to claim 4 wherein said address signal isbinary in character and each binary bit is transmitted through aseparate conductor.

6. The apparatus according to claim 5 wherein each binary bit is carriedon both a bit conductor and a notbit conductor and wherein redundancychecking means is provided to check the bit-signal for correspondencewith the non-bit signal.

7. Apparatus according to claim 4 wherein said multi-conductor cable islooped back upon itself so that two alternate paths are provided fortransmitting said computer signal to said control station.

8. The apparatus according to claim 1 wherein the control station is adirect digital control station which actuates means for controlling saidsystem variable and whereby the value of said variable is measured by asensor which transmits said value to the computer and not to anylocalized control station.

9. The apparatus according to claim 1 wherein the control station is ananalog control station and wherein the signal received from said memoryadjusts a set point on an analog control loop and wherein the value ofsaid system variable is determined by a sensor which transmits saidvalue back to said analog control station.

10. In a process for converting output from a digital computer tooperate a control system by changing the digital control point value inthe memory of a desired control station via a common cable means towhich a plurality of said control stations are connected, theimprovement comprising:

a. transmitting via said common cable an address signal which causes thedesired control station to become responsive to a command signal,

b. transmitting a command signal to zero the set point value of saiddesired control station, and

c. thereafter transmitting a command signal to insert the new digitalcontrol point value into the memory of said desired control station.

II. A process according to claim including the step of said computertransmitting signals from said comparator by transmitting each digit ofsaid signal over a separate conductor of a multi-conductor cable andwherein said signals are transmitted to a plurality of said comparators,each connected to the conductors of said multi-conductor cable.

12. A process according to claim 11 wherein said address signal isbinary in character and each binary bit is carried by a separateconductor.

13. A process according to claim 12 wherein each binary bit is carriedon both a bit conductor and a not-bit conductor and wherein redundancychecking means is provided to check the bit-signal for correspondencewith the non-bit signal.

14. A process according to claim 10 wherein the control station is ananalog control station and including the additional step of the signalreceived from said memory causing adjustment of a set point on an analogcontrol loop, and determining the value of said system variable by asensor which transmits said value back to said analog control station.

15. A process according to claim 10 including the additional step ofsaid memory continuously transmitting said new digital control values tosaid control station until said digital control value is zeroed inresponse to a zero co m d i al from said c uter, sai zero commar ifi sig nal b i ng accompanie or prece ed by a proper address signal.

16. The process of claim 15 wherein the transmission of said signal fromsaid memory to said control station is limited by rate of changelimiting means so that the digital control value signal inputted to saidcontrol sta tion changes at a rate not in excess of a predeterminedmaximum rate of change whereby said new digital control value isgradually applied to said system.

17. A process according to claim 1 wherein the control station is adirect digital control station and the control station actuates meansfor controlling said system variable including the additional step ofmeasuring the value of said variable by a sensor which transmits saidvalue to the computer and not to any localized control station.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No.3,693,163 Dated Sept. 19, 1972 lnventofls) I.D.Johnson, E.P.Kaufmann,M.G.Togneri It is certified that error appears in the above-identifiedpatent and that said Letters Patent are hereby corrected as shown below:

Col. 3, line 31: "the memory of computer 127" should read the memory ofcomputer l2)- Col. 9, line 17: (1966914 manu" should read:

-- (1966) NOR-gates can be Model No. 914 manu- Col. 10, line 33: "d."should read e.

Si ned and sealed this 1st day of May 1973.

(SEAL) lttest:

EDWARD M. FLETCHER, JR. ROBERT GOTTSCHALK Attesting Officer Commissionerof Patents DEW PC7-1050 USCOMM-DC scan-Pen 9 U S GOVEPNHENY PRlNYlNGOFFICE 1,59 O-]65-Jll.

1. Apparatus for interfacing a digital computer with a control systemcomprising in combination, a. a digital computer controlling the systemin response to inputs received from various sensors indicative ofconditions within various points in the system, said computer havingmeans for outputting a selective digital address signal and associatedcommand signals, b. a multiplicity of control stations, each of saidcontrol stations having means for controlling at least one variable ofthe system in response to one of said command signals indicative of adesired control point value for that variable, c. common cable means forreceiving said selected digital address signal and associated commandsignals outputted by said computer means, said cable means beingconnected to a plurality of said control stations, d. prewired addressmeans in each of said control stations which is distinct from similarprewired addresses of other of said control stations, d. comparatormeans in each said control stations for comparing the address outputtedby said computer with said prewired address, f. address logic means forpermitting said digital command signals to be transmitted from saidcomputer to said memory means, within a particular control station,when, and only when, said command signals are associated with an addresssignal corresponding to the prewired address of said particular controlstation, g. zeroing means in each said control station for zeroing saidmemory means in response to an appropriate zero command signal from saidcomputer, h. memory means in each said control station for storing saiddesired control point value transmitted from said computer.
 2. Theapparatus of claim 1 wherein there is further provided: i. rate ofchange limiting means for controlling the transmission of said signalfrom said memory to said control station so that the control valuesignal inputted to said control station changes at a rate not in excessof a predetermined maximum rate of change whereby said new digitalcontrol value is gradually applied to said system.
 3. The apparatusaccording to claim 2 wherein the rate of change limiting means comprisescapacitive means having a preselected time constant corresponding to thedesired maximum rate of change.
 4. The apparatus according to claim 1wherein the signal outputted by said computer is transmitted to saidcomparator by means of a multi-conductor cable connected to a pluralityof said address comparators.
 5. The apparatus according to claim 4wherein said address signal is binary in character and each binary bitis transmitted through a separate conductor.
 6. The apparatus accordingto claim 5 wherein each binary bit is carried on both a bit conductorand a not-bit conductor and wherein redundancy checking means isprovided to check the bit-signal for correspondence with the non-bitsignal.
 7. Apparatus according to claim 4 wherein said multi-conductorcable is looped back upon itself so that two alternate paths areprovided for transmitting said computer signal to said control station.8. The apparatus according to claim 1 wherein the control station is adirect digital control station which actuates means for controlling saidsystem variable and whereby the value of said variable is measured by asensor which transmits said value to the computer and not to anylocalized control station.
 9. The apparatus according to claim 1 whereinthe control station is an analog control station and wherein the signalreCeived from said memory adjusts a set point on an analog control loopand wherein the value of said system variable is determined by a sensorwhich transmits said value back to said analog control station.
 10. In aprocess for converting output from a digital computer to operate acontrol system by changing the digital control point value in the memoryof a desired control station via a common cable means to which aplurality of said control stations are connected, the improvementcomprising: a. transmitting via said common cable an address signalwhich causes the desired control station to become responsive to acommand signal, b. transmitting a command signal to zero the set pointvalue of said desired control station, and c. thereafter transmitting acommand signal to insert the new digital control point value into thememory of said desired control station.
 11. A process according to claim10 including the step of said computer transmitting signals from saidcomparator by transmitting each digit of said signal over a separateconductor of a multi-conductor cable and wherein said signals aretransmitted to a plurality of said comparators, each connected to theconductors of said multi-conductor cable.
 12. A process according toclaim 11 wherein said address signal is binary in character and eachbinary bit is carried by a separate conductor.
 13. A process accordingto claim 12 wherein each binary bit is carried on both a bit conductorand a not-bit conductor and wherein redundancy checking means isprovided to check the bit-signal for correspondence with the non-bitsignal.
 14. A process according to claim 10 wherein the control stationis an analog control station and including the additional step of thesignal received from said memory causing adjustment of a set point on ananalog control loop, and determining the value of said system variableby a sensor which transmits said value back to said analog controlstation.
 15. A process according to claim 10 including the additionalstep of said memory continuously transmitting said new digital controlvalues to said control station until said digital control value iszeroed in response to a zero command signal from said computer, saidzero command signal being accompanied by or preceded by a proper addresssignal.
 16. The process of claim 15 wherein the transmission of saidsignal from said memory to said control station is limited by rate ofchange limiting means so that the digital control value signal inputtedto said control station changes at a rate not in excess of apredetermined maximum rate of change whereby said new digital controlvalue is gradually applied to said system.
 17. A process according toclaim 1 wherein the control station is a direct digital control stationand the control station actuates means for controlling said systemvariable including the additional step of measuring the value of saidvariable by a sensor which transmits said value to the computer and notto any localized control station.